module intgen
	(clock, resetn, load, sclr, INT, INTMASK, int_masked);
input			clock, resetn;
input			load, sclr;
input	[7:0]	INT, INTMASK;
output			int_masked;

reg		[7:0]	INTREG, INTMASKREG;

assign			int_masked = &(INTREG | ~INTMASKREG);

always @(posedge clock or negedge resetn)
begin
	if (!resetn)	INTREG <= 0;
	else			INTREG <= INT;
end

always @(posedge clock or negedge resetn)
begin
	if (!resetn)	INTMASKREG <= 0;
	else if (sclr)	INTMASKREG <= 0;
	else if (load)	INTMASKREG <= INTMASK;
end

endmodule